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AMD Versal Premium Gen 2 MoP: 32GB In-Package LPDDR5X, 288GB/s, 60% Less Board Area

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AMD Versal Premium Gen 2 MoP: 32GB In-Package LPDDR5X, 288GB/s, 60% Less Board Area

July 10, 2026
AMD has unveiled its new Versal Premium Gen 2 Memory-on-Package (MoP) adaptive SoCs, featuring on-package integrated LPDDR5X memory to boost memory bandwidth, cut down board layout complexity, and shrink overall device footprint. Optimized for scenarios with tight power and space limitations yet demanding high memory throughput, the new chips serve a wide range of fields including networking, physical AI processing, aerospace and defense, test and measurement, and professional video infrastructure.

Breaking away from conventional SoC designs that depend on discrete external DRAM modules, the Versal Premium Gen 2 MoP architecture integrates up to 32GB of LPDDR5X memory directly within the chip package, delivering a peak memory bandwidth of 288GB/s. According to AMD’s internal testing based on the 2VP3622 device, this MoP implementation reduces board area by up to 60% versus standard Versal Premium Gen 2 SoCs paired with external memory, while greatly simplifying complex high-speed memory routing layouts.

latest company case about AMD Versal Premium Gen 2 MoP: 32GB In-Package LPDDR5X, 288GB/s, 60% Less Board Area  0

This integrated memory design effectively elevates data bandwidth, lowers access latency, and cuts power draw compared to traditional board-mounted memory solutions. Removing external LPDDR5X circuitry streamlines PCB design workflows, reduces repeated validation workloads, and shortens overall product development timelines for hardware designers.

Optimized for Edge and Compact Embedded Deployments


AMD tailors this platform for space-constrained embedded and edge systems. Its compact form factor supports compliance with mainstream industry standards such as EDSFF and 3U VPX, fitting the strict thermal and mechanical constraints of telecom and defense-grade hardware platforms.

The SoCs embed native PCIe 6.0 and CXL 3.1 hard IP running at 64GT/s, enabling ultra-high-speed interconnects with AMD EPYC processors and other mainstream host chips. Paired with LPDDR5X memory clocked at up to 9,000Mb/s, the platform easily handles data-heavy workloads. It also allows system architects to flexibly expand system memory via CXL-based memory pooling and extension technologies.

Built for long-lifecycle industrial deployments, the Versal Premium Gen 2 MoP family supports an extended industrial temperature range of -40°C to 110°C and guarantees over 15 years of product supply availability. Adopting LPDDR5X instead of traditional HBM also avoids the frequent refresh cycles typical of data center-grade memory, minimizing hardware redesign risks caused by component phase-outs and supply fluctuations.

Built-In End-to-End Security Features


The platform comes equipped with comprehensive native security capabilities. PCIe Integrity and Data Encryption (IDE), a new feature introduced alongside PCIe 6.0, safeguards data transmission across high-speed PCIe links. Integrated DDR memory encryption protects in-memory data without occupying device programmable logic resources. Additionally, dedicated 400G high-speed crypto engines deliver secure, high-throughput data processing for mission-critical workloads.

AMD’s core design goal for the new MoP series is to eliminate long-standing engineering tradeoffs between memory bandwidth, physical footprint, power efficiency, and product service life. By integrating memory into the adaptive SoC package, the new lineup empowers developers to build higher-performance embedded systems, reduce board-level engineering overhead, and accelerate product rollouts.
Development support is available immediately, leveraging currently shipping standard Versal Premium Gen 2 devices, mature Vivado and Vitis development toolchains, compatible IP cores, and validated reference designs. AMD plans to release engineering samples of the Versal Premium Gen 2 MoP devices by late 2026, with formal mass production shipments slated for the second half of 2027.

Beijing Qianxing Jietong Technology Co., Ltd.
Sandy Yang/Global Strategy Director
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Email: yangyd@qianxingdata.com
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