South Korean fabless semiconductor firm Panmnesia is advancing CXL and UAL/Ethernet integration. It has launched a PCIe-CXL fusion chip to support future CXL/UAL unification. Meanwhile, Meta deploys legacy DRAM on new servers via CXL to expand memory capacity and boost system speed.
Panmnesia focuses on CXL controller and switch development. The Compute Express Link (CXL) is an out-of-chassis PCIe bus extension, originally based on PCIe 5.0 and now compatible with PCIe 6.0 and 7.0 standards.Panmnesia CEO Myoungsoo Jung noted that the industry long believed CPU-attached switches would induce unacceptable memory-access latency, making scalable Multi-Headed Devices (MHDs) impractical and forcing direct MHD deployment. He clarified that such latency issues stem from early CXL immaturity rather than inherent standard limitations, and will fade with ecosystem maturation. The firm’s next-gen CXL controller-powered switches deliver scalable, low-latency and stable performance.
Panmnesia will showcase its optimized next-gen CXL controller and Port-Based Routing (PBR)-enabled switch at ISCA 2026. Early CXL designs reused PCIe IP with independent layer buffers and separate timing control, causing heavy cross-layer synchronization overhead and additional latency.
Panmnesia’s new controller adopts cross-layer shared buffers to eliminate most overheads, with further layer-specific optimizations for lower latency. Traditional PCIe and early CXL rely on Hierarchy-Based Routing (HBR) limited to tree topologies, while PBR routes data via unique device port IDs to enable flexible arbitrary topologies. The new switch supports both PBR and HBR modes.
Conventional CXL memory expansion uses CPU-direct MHDs with limited scalability. Panmnesia’s fabric switch enables large-scale memory expansion with comparable latency and higher system bandwidth, stably supporting up to 64 connected nodes in tests.
Panmnesia has rolled out pre-release PCIe 6.4-CXL 3.2 fusion switch chips. Its upgraded IP integrates CXL 4.0 features, offering a complete PCIe 7.0-CXL 4.0 combo solution.Panmnesia and Meta will present back-to-back papers at the June 29 ISCA 2026 Industry Session. Panmnesia’s paper discusses a silicon-proven low-latency CXL controller and PBR switch for memory-centric fabrics. Meta’s paper introduces Vistara, its full-stack CXL deployment solution for hyperscale data centers.
Facing tight memory supply, rising costs and delayed deliveries, Meta’s Vistara team proposes reusing retired DDR4 DIMMs alongside server-local DDR5 memory via standard CXL interconnects. This approach enables near-zero-cost memory expansion, higher operational performance and lower carbon emissions.
Slow industry CXL adoption is caused by CXL memory’s low bandwidth, high latency and runtime overhead. Meta’s production data shows CXL expanded memory delivers 10× lower bandwidth and 60% higher latency than local memory. Moreover, most commercial CXL solutions integrate DRAM with controllers and lack DDR4 support, blocking legacy memory reuse.
Meta resolves these pain points through hardware-software co-design. It developed the custom Vistara CXL ASIC optimized for DRAM reuse, power efficiency and low latency. On the software side, an enhanced Transparent Page Placement (TPP) solution dynamically adjusts local/expanded memory ratios and automates workload-specific configurations, disabling CXL memory for latency-sensitive workloads.
The paper fully validates CXL’s practical value and significant performance gains across diverse workloads. Meta’s solution cuts disaggregated ML inference server deployment by 25% and reduces distributed cache average latency by 29%.
ISCA 2026 runs from June 27 to July 1 in Raleigh, USA. Panmnesia partners can access pre-release PCIe 6.4-CXL 3.2 fusion switch chips, pilot systems and PCIe 7.0-CXL 4.0 combo IP.
Footnote: CXL switches bridge GPUs, memory and other system devices. PBR supports flexible arbitrary network topologies, outperforming HBR’s rigid tree structure and improving architectural flexibility. Ultra Accelerator Link (UAL), a rival to NVIDIA NVLink, enables cross-vendor high-speed AI accelerator interconnection. Its alliance includes AMD, AWS, Google, Microsoft, Meta, Panmnesia and other key industry players.
Beijing Qianxing Jietong Technology Co., Ltd.
Sandy Yang/Global Strategy Director
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Email: yangyd@qianxingdata.com
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