Kioxia and SanDisk have begun sampling their tenth-generation 332-layer BiCS 3D NAND memory chips.
The new 1 Tbit TLC (3 bits per cell) chips are designed for enterprise and data center SSD deployment. This new iteration succeeds the 218-layer BiCS 8 flash memory. Besides a 52% rise in stacking layers, the duo has adopted two key upgrades: CMOS directly Bonded to Array (CBA) and On-Pitch Select Gate Drain (OPS) technologies. The CBA process fabricates logic and NAND cell wafers separately before bonding them together, while OPS trims bit line length and cuts word line capacitance by eliminating redundant memory holes.
Enhanced lateral scaling and an additional 114 stacked layers jointly boost the chip’s cell density. Its 4.8 Gbit/s interface speed is 33% faster than the previous BiCS 8 generation. Kioxia also confirms 18% improved write power efficiency and 30% better read power efficiency, effectively lowering overall power draw.
Kioxia’s intermediate BiCS 9 technology leverages 218-layer BiCS 8 3D NAND cells paired with an independent CMOS logic layer, delivering better performance than the original BiCS 8 circuitry. Equipped with Toggle DDR6.0 interface and Separate Command Address (SCA) protocol, BiCS 10 achieves a 4.8 Gbit/s transfer rate, representing the same 33% speed upgrade over BiCS 8.
Sandisk and Kioxia's BiCS 10 NAND
Mass production of BiCS 10 is scheduled to launch next year at Japan’s Kitakami Plant 2 in Iwate Prefecture. As part of their joint venture, both firms share the fab’s output and are currently shipping BiCS 10 samples. The 332-layer platform also supports upcoming QLC (4 bits per cell) variants, which can lift chip capacity by one-third.The BiCS 10 architecture stacks three sets of 100+ layer NAND strings, instead of adopting a monolithic 332-layer chip design.
Kioxia anticipates sustained strong NAND demand driven by the rising popularity of agentic AI and AI-powered robotics. CEO Hiroo Ota signaled potential capacity expansion during a Japanese media event, stating the company will fully cater to ongoing market growth.
In the competitive landscape, SK Hynix’s ninth-generation 3D NAND features 321 layers with a triple-string stacking structure. Samsung’s tenth-generation V NAND reaches 400 layers, adopting a Cell-on-Periphery (CoP) architecture with separate logic and memory wafers to produce 1 Tbit dies, similar to Kioxia’s design. Micron currently offers 276-layer NAND, with no official updates on future layer roadmap. China’s YMTC is poised to release its 300-layer-class 3D NAND technology in the near future.
Beijing Qianxing Jietong Technology Co., Ltd.
Sandy Yang/Global Strategy Director
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Email: yangyd@qianxingdata.com
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