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IBM has unveiled an innovative 0.7nm (7-angstrom) transistor architecture, recognized as the industry’s first sub-1nm semiconductor technology. As the semiconductor sector continues to break the physical limits of conventional transistor scaling, this research achievement marks a key scientific and technological breakthrough in the industry.
IBM Nanostack Technology
This experimental technology enables the integration of nearly 100 billion transistors on a fingernail-sized chip, nearly doubling the transistor density of IBM’s 2nm chip technology first launched in 2021. According to IBM, tailored to the optimization priorities of practical application scenarios, the new architecture can deliver up to 50% higher performance or up to 70% improved energy efficiency compared with the existing 2nm process.
The core of this technology launch is an innovative three-dimensional transistor architecture named "nanostack", which realizes sub-1nm logic chip scaling for the first time in the industry.
Innovative 3D Nanostack Architecture
Moving beyond the traditional solution of simply shrinking transistor dimensions, this technology vertically stacks and staggers nanosheet transistors via a 3D integration process. This innovative approach not only greatly boosts transistor integration density, but also allows different materials to be deployed in each layer, enabling independent and precise optimization of chip performance and power consumption within the stacked structure.
IBM’s research team has completed experimental validation of the architecture through ultra-thin dielectric bonding for CMOS integration, dual-channel engineering optimization, and testing of fully functional CMOS inverter circuits. A series of test results have verified that the architecture is physically manufacturable and can steadily support the operation of various computational workloads.
Jay Gambetta, Director of IBM Research, stated that this breakthrough is not a simple upgrade of transistor scaling, but a disruptive innovation in chip manufacturing processes. Operating at process scales close to the atomic level, the architecture delivers simultaneous improvements in both chip performance and energy efficiency.
SRAM Scaling Optimization for AI Computing Power
At the 2026 Symposium on VLSI Technology and Circuits, IBM released another supporting research result: the nanostack architecture achieves approximately 40% SRAM scaling. For AI accelerators and high-performance computing systems, overall system performance is frequently constrained by memory bandwidth and storage capacity. Continuous improvements in memory density have therefore become increasingly critical for advanced computing applications.
These SRAM innovations empower chip designers to develop more efficient processors while addressing the growing memory requirements of generative AI, cloud infrastructure, and data-heavy workloads.
Extending the Semiconductor Technology Roadmap
While modern process nodes no longer strictly correspond to specific physical transistor dimensions, IBM’s 0.7nm technology opens up a viable path for continuous logic scaling into the angstrom era. The firm believes the nanostack methodology can sustain further transistor scaling for at least another decade beyond today’s state-of-the-art processes.
The research was jointly conducted at IBM’s semiconductor research center in Albany, New York, together with industrial partners. The facility is set to accommodate ASML’s High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography system, a pivotal technology for upcoming advanced process generations. IBM and its collaborators have already verified functional devices fabricated using High NA EUV processes.
Production Outlook
IBM continues to solidify its position as a leading semiconductor research institution, with extensive contributions covering silicon process innovation, AI hardware design, and quantum computing development. The company has recently announced the launch of Anderon, an independent quantum foundry dedicated to quantum wafer manufacturing.
Though the 0.7nm breakthrough currently remains a research achievement, IBM indicates that commercial manufacturing based on the nanostack architecture may be realized within the next five years, laying a solid foundation for mass-producible sub-1nm semiconductor technology.
Beijing Qianxing Jietong Technology Co., Ltd.
Sandy Yang/Global Strategy Director
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Sandy Yang/Global Strategy Director
WhatsApp / WeChat: +86 13426366826
Email: yangyd@qianxingdata.com
Website: www.qianxingdata.com/www.storagesserver.com
Business Focus:
ICT Product Distribution/System Integration & Services/Infrastructure Solutions
With 20+ years of IT distribution experience, we partner with leading global brands to deliver reliable products and professional services.
“Using Technology to Build an Intelligent World”Your Trusted ICT Product Service Provider!